The present invention relates to packaging of integrated circuits and, more particularly, to encapsulating semiconductor dies with an encapsulation material.
Semiconductor packages are containers for integrated circuits formed on a semiconductor die. Typically, the die is encapsulated with an encapsulant material such as a plastic resin that forms a protective exterior surface of the semiconductor package. The package has electrical interconnects between contact pads of the integrated circuit on the die and exposed input/output (I/O) pins for interconnecting the integrated circuit with external circuitry.
In the process of encapsulating the die, during curing of the encapsulant, the properties of the encapsulant material can cause the die to drift and move position. This post-encapsulation cure, die drift, or skew results in the die having a different actual post-encapsulation position than when it was initially placed on a panel before the encapsulation process. Die drift complicates later high precision processing steps, such as interconnecting die bonding pads or connection points of the die with interconnects, feature and trace positioning on photo masks, and aperture positioning on printing or ball drop screens for connection between die bonding pads to metal layers and bumps or balls. Any misalignment or miscoupling between the interconnects and the die pads may result in device and package failure, lowering manufacturing yield.
In an attempt to compensate for die drift, a pick and place position of the die on the surface support panel or frame is determined before encapsulation using empirical data. However, relying on die pitch compensation still results in misalignments between connection points and interconnects. In particular, the error associated with die pitch compensation has been increasing due to the industry trend for a smaller chip footprint yet with an increased density of connection points and interconnects.
In an attempt to overcome the limitations of die pitch compensation, a sheet of perforated single plane metal known as an embedded ground plane plate or frame has been implemented in the die encapsulation process. The embedded ground plane plate is positioned on top of and extends across the entire area or breadth of the mold or encapsulating area of the panel or substrate surface. A die is placed on the substrate surface in each perforated area of the embedded ground plane plate. Although in the advent of embedded ground plane plates some improvements have been achieved in reducing die drift or skew, there are limitations with the use of conventional embedded ground planes. During assembly, a single embedded ground plane plate or sheet is used. Often, however, it is desirable to have different thicknesses and materials of the embedded ground plane plate around different sized semiconductor dies with different sizes and dimensions and electrical, thermal and mechanical requirements in a single batch.
Another limitation with conventional embedded ground plane plates is panel warpage caused by an imbalance of panel expansion after encapsulation cure between the embedded components of the panel in the encapsulant. As the embedded ground plane plate extends across the entire area of the surface of the panel, when the panel warps, the panel is not able to be adequately held to a wafer chuck table by a vacuum without additional assistance such as a mechanical stiffener. However, mounting a mechanical stiffener to the panel introduces additional cost and processing time.
Additionally, with traditional embedded ground plane plates there can be package reliability failure due to delamination propagation that arises at the embedded ground plane plate to the encapsulant interface and embedded ground plane plate to dielectric interface during package sawing at singulation, which contributes to lower processing yield. Accordingly, there is a need for addressing or at least alleviating the above limitations and problems.